//==========================================================================
// Copyright (c) 2000-2008,  Elastos, Inc.  All Rights Reserved.
//==========================================================================

#ifndef __ELASTOS_EXCEPTION_H__
#define __ELASTOS_EXCEPTION_H__

enum {
// External event (bit 0). When set, indicates that an event external to the
// program caused the exception, such as a hardware interrupt.
    ErrorCode_EXT               = __32BIT(0),

// IDT Descriptor location (bit 1). When set, indicates that the index portion
// of the error code refers to a gate descriptor in the IDT; when clear,
// indicates that the index refers to a descriptor in the GDT or the current LDT.
    ErrorCode_IDT               = __32BIT(1),

// GDT/LDT (bit 2). Only used when the IDT flag is clear. When set, the TI flag
// indicates that the index portion of the error code refers to a segment or
// gate descriptor in the LDT; when clear, it indicates that the index refers
// to a descriptor in the current GDT.
    ErrorCode_TI                = __32BIT(2),
};

enum {
// The processor provides the page-fault handler with two items of information
// to aid in diagnosing the exception and recovering from it:
// An error code on the stack. The error code for a page fault has a format
// different from that for other exceptions. The error code tells the exception
// handler four things:
//  The P flag indicates whether the exception was due to a not-present page (0)
//  or to either an access rights violation or the use of a reserved bit (1).
//      0 The fault was caused by a nonpresent page.
//      1 The fault was caused by a page-level protection violation.
    PageFault_ErrorCode_P       = __32BIT(0),

//  The W/R flag indicates whether the memory access that caused the exception
//  was a read (0) or write (1).
//      0 The access causing the fault was a read.
//      1 The access causing the fault was a write.
    PageFault_ErrorCode_WR      = __32BIT(1),

//  The U/S flag indicates whether the processor was executing at user mode (1)
//  or supervisor mode (0) at the time of the exception.
//      0 The access causing the fault originated when the processor
//          was executing in supervisor mode.
//      1 The access causing the fault originated when the processor
//          was executing in user mode.
    PageFault_ErrorCode_US      = __32BIT(2),

//  The RSVD flag indicates that the processor detected 1s in reserved bits of
//  the page directory, when the PSE or PAE flags in control register CR4 are
//  set to 1. (The PSE flag is only available in the P6 family and Pentium
//  processors, and the PAE flag is only available on the P6 family processors.
//  In earlier Intel Architecture processor families, the bit position of the
//  RSVD flag is reserved.)
//      0 The fault was not caused by a reserved bit violation.
//      1 The page fault occured because a 1 was detected in one of the
//          reserved bit positions of a page table entry or directory entry
//          that was marked present.
    PageFault_ErrorCode_RSVD    = __32BIT(3),
};

typedef enum ExceptionVector {
    ExceptionVector_DivideError                 = 0,
    ExceptionVector_Debug                       = 1,
    ExceptionVector_NMI                         = 2,
    ExceptionVector_Breakpoint                  = 3,
    ExceptionVector_Overflow                    = 4,
    ExceptionVector_BoundRangeExceeded          = 5,
    ExceptionVector_InvalidOpcode               = 6,
    ExceptionVector_DeviceNotAvailable          = 7,
    ExceptionVector_DoubleFault                 = 8,
    ExceptionVector_CoprocessorSegmentOverrun   = 9,
    ExceptionVector_InvalidTSS                  = 10,
    ExceptionVector_SegmentNotPresent           = 11,
    ExceptionVector_StackFault                  = 12,
    ExceptionVector_GeneralProtection           = 13,
    ExceptionVector_PageFault                   = 14,
    // 15: Intel reserved
    ExceptionVector_FloatingPointError          = 16,
    ExceptionVector_AlignmentCheck              = 17,
} ExceptionVector;

EXTERN DECL_CODEINIT void CDECL InitExceptions();

#endif // __ELASTOS_EXCEPTION_H__
